QG5000XSL9TH Datasheet, PDF (265/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
8
0
70h
Intel 5000P Chipset
Bit
2:0
Attr Default
Description
RO
000
MPLSS: Max_Payload_Size Supported
This field indicates the maximum payload size that the CB integrated device can
support.
000: 128B max payload size
others- Reserved
3.10.18 PEXDEVCTRL - Device Control Register
Device:
Function:
Offset:
Version:
8
0
74h
Intel 5000P Chipset
Bit Attr Default
Description
15
RV
0
14:12 RO
000
11
RW
1
10
RO
0
9
RO
0
8
RO
0
7:5
RW
000
Reserved
MRRS: Max_Read_Request_Size
Since the DMA Engine device does not issue read requests on a PCI Express
interface, this field is irrelevant. Hardwired to 0h
ENNOSNP: Enable No Snoop
1: Setting this bit enables the DMA Engine device to issue requests with the No
Snoop attribute.
0: Clearing this bit behaves as a global disable when the corresponding capability is
enabled for source/destination snoop control in the DMA’s descriptor’s Desc_Control
field.
APPME: Auxiliary Power PM Enable
The DMA Engine device does not implement auxiliary power so setting this bit has
no effect. Hardwired to 0h
PFEN: Phantom Functions Enable
The DMA Engine device does not implement phantom functions so setting this bit
has no effect. Hardwired to 0h
ETFEN: Extended Tag Field Enable:
The DMA Engine device does not implement extended tags so setting this bit has no
effect.
MPS: Max_Payload_Size:
The DMA Engine device must not generate packets on any PCI Express interface
which exceeds the length allowed with this field.
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
4
RO
0
101: 4096B max payload size
Note: This field has no impact internally to Intel 5000P Chipset MCH and the
maximum payload size of the TLPs that appear on the PCI Express port is
governed by the PEXDEVCTRL.MPS for that port defined in Table 3.8.11.4
ENRORD: Enable Relaxed Ordering
No relaxed ordering is supported by Intel 5000P Chipset MCH. Hardwired to 0h.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
265