QG5000XSL9TH Datasheet, PDF (52/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.5.2
CFGDAT: Configuration Data Register
CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This
register is only accessed if there is an access to I/O address, CFCh on the processor bus
and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O
access define how many configuration bytes are accessed.
Table 3-6.
I/O Address: CFCh
Bit Attr Default
31:0 RW
0
Description
Configuration Data Window
The data written or read to the configuration register (if any) specified by
CFGADR
3.6
MCH Fixed Memory Mapped Registers
These registers are mapped into the fixed chipset specific range located from FE60
0000h - FE6F FFFFh.These appear at fixed addresses to support the boot process.
These registers also appear in the regular PCI Express configuration space.
The following table defines the memory address of the registers in this region.
Table 3-7.
Mapping for Fixed Memory Mapped Registers
Register
BOFL0
BOFL1
BOFL2
BOFL3
SPAD0
SPAD1
SPAD2
SPAD3
SPADS0
SPADS1
SPADS2
SPADS3
AMBASE[31:0]
AMBASE[63:32]
HECBASE
Memory Address
FE60_C000
FE60_C400
FE60_C800
FE60_CC00
FE60_D000
FE60_D400
FE60_D800
FE60_DC00
FE60_E000
FE60_E400
FE60_E800
FE60_EC00
FE61_4800
FE61_4C00
FE61_6400
52
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet