QG5000XSL9TH Datasheet, PDF (10/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

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Device 5-7, Function 0: PCI Express Intel IBIST Registers .......................................64
Device 9, Function 0: AMB Switching Window Registers ..........................................64
Device 16, Function 0: Processor Bus, Boot, and Interrupt ......................................65
Device 16, Function 1: Memory Branch Map, Control, Errors ....................................66
Device 16, Function 2: RAS .................................................................................67
Device 21, 22, Function 0: FB-DIMM Map, Control, RAS ..........................................68
Device 21, Function 0: FB-DIMM 0 Intel IBIST Registers .........................................69
Device 21, Function 0: FB-DIMM 1 IBST Registers .................................................70
Device 22, Function 0: FB-DIMM 2 IBST Registers ..................................................71
Device 22, Function 0: FB-DIMM 3 Intel IBIST Registers .........................................72
Address Mapping Registers .................................................................................81
Register Offsets in AMB Memory Mapped Registers Region ......................................92
XTPR Index .......................................................................................................99
When will an Intel 5000X Chipset PCI Express* Device be Accessible? .................... 100
Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data
Parity Error RAS Handling ................................................................................. 113
GIO Port Mode Selection ................................................................................... 125
IV Handling and Processing by MCH ................................................................... 137
Maximum Link Width Default Value for Different PCI Express Ports ......................... 147
Negotiated Link Width For Different PCI Express Ports After Training ...................... 150
Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields.......... 196
FB-DIMM to Host Gear Ratio Mux ....................................................................... 201
FB-DIMM to Host Gear Ratio Mux ....................................................................... 201
Host to FB-DIMM Gear Ratio Mux Select.............................................................. 202
FB-DIMM Host Data Cycle Valid Mux Select ......................................................... 203
FB-DIMM to Host Flow Control Mux Select ........................................................... 204
FB-DIMM Bubble Mux Select.............................................................................. 204
FB-DIMM to Host Double Config Mux Select ......................................................... 205
Optimum TREF values as a function of core: FBD gear ratios (in FBD Super frames) . 207
Timing Characteristics of ERRPER....................................................................... 208
Interleaving of an address is governed by MIR[i].................................................. 209
NRECFBD Mapping Information.......................................................................... 220
ECC Locator Mapping Information ...................................................................... 222
IV Vector Table for DMA Errors and Interrupts ..................................................... 263
Memory Segments and Their Attributes .............................................................. 280
PAM Settings................................................................................................... 282
Low Memory Mapped I/O1 ................................................................................ 285
I/O APIC Address Mapping ................................................................................ 287
Intel 5000X chipset MCH Memory Mapping Registers ............................................ 289
Address Disposition for Processor....................................................................... 290
Enabled SMM Ranges ....................................................................................... 292
SMM Memory Region Access Control from Processor ............................................. 292
Decoding Processor Requests to SMM and VGA Spaces ......................................... 293
Address Disposition for Inbound Transactions ...................................................... 294
DBI[3:0]# / Data Bit Correspondence................................................................. 300
Snoop Filter Physical Address Partitioning ........................................................... 304
FSB transaction encoding qualification for SF look up............................................ 304
Snoop Filter Entry ............................................................................................ 304
Minimum System Memory Configurations & Upgrade Increments............................ 306
Maximum 16 DIMM System Memory Configurations.............................................. 307
Maximum 16 DIMM System Memory Configurations.............................................. 307
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet