QG5000XSL9TH Datasheet, PDF (408/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Electrical Characteristics
Notes:
1. Refer to chapter 5 of Intel^® 5000P chipset/Intel^® 5000V chipset and Intel^® 5000X chipset External Design Specification
(EDS) Addendum.
2. Crossing voltage is defined as the instantaneous voltage when the rising edge of CORECLKP is equal to the falling edge of
CORECLKN.
3. Overshoot is defined as the absolute value of the maximum voltage.
4. Undershoot is defined as the absolute value of the minimum voltage.
5. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback. Both maximum Rising and Falling Ringbacks should not cross the threshold region.
6. Threshold Region is defined as a region centered around the crossing point voltage in which the differential receiver switches.
It includes input threshold hysteresis.
7. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
8. VHavg (the average of V_IH) can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
7.2.2 FSB Interface DC Characteristics
Table 7-5. FSB Interface DC Characteristics
Symbol
V_IL
V_IH
V_OL
V_OH
I_OL
I_LI
I_LO
R_on
Signal
Group
• (a) (b)
• (a) (b)
• (a) (c)
• (a) (c)
• (a) (c)
• (a) (b)
• (a) (b)
•
Parameter
Host AGTL+ Input Low
Voltage
Host AGTL+ Input High
Voltage
Host AGTL+ Output Low
Voltage
Host AGTL+ Output High
Voltage
Host AGTL+ Output Low
Current
Host AGTL+ Input Leakage
Current
Host AGTL+ Output
Leakage Current
Buffer on Resistance
Min
0
GTLREF +
(0.1 × V_TT)
0.90 x V_TT
n/a
n/a
7
Nom
Max
GTLREF –
(0.1 × V_TT)
V_TT
0.4
Unit
V
Note
s
1, 2
V
1, 3
V
V_TT
V
V_TT / (0.50 x
mA
R_{tt_min} + R_{on_min})
+/- 200
uA
4
8
5, 6
+/- 200
uA
5, 6
11
Ω
GTLREF
R_TT
• (e)
•
Host Bus Reference
Voltage
(0.98 x 0.67) x V_TT 0.67 x (1.02 x 0.67) x V_TT
V
1
V_TT
Host Termination
45
50
55
Ω
7
Resistance Common Clock,
Async on Stripline
Notes:
1. GTLREF is equivalent to FSBxFSBVREF. GTLREF is generated from V_TT on the baseboard by a voltage divider or 1%
resistors.
2. V_IL is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
3. V_IH is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
4. V_IH and V_OH may experience excursions above V_CC. However, input signal drivers must comply with the signal quality
specifications chapter in the document.
5. Leakage to VSS with land held at V_TT.
6. Leakage to V_TT with land held at 300 mV.
7. Use 50 ohm ±15% for all Microstrip.
8. I_OLis defined as current when Output Low. The formula computes the total current drawn by the driver from VR (Voltage
Regulator). Half of the total current goes through RTT on the chipset, and another half goes through the RTT on the CPU (the
End-Bus-Agency).
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet