QG5000XSL9TH Datasheet, PDF (113/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
1Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Eh
Intel 5000Z Chipset
4-7
0
1Eh
Intel 5000P Chipset
Bit
Attr
12
RWC
11
RWC
10:9 RO
8
RWC
7
RO
6
RV
5
RO
4:0
RV
Default
0
0
00
0
0
0
0
0h
Description
SRTAS: Received Target Abort Status
This bit is set when the PCI Express port receives a Completion with
“Completer Abort” Status.
SSTAS: Signaled Target Abort
This bit is set when the PCI Express port completes a request with “Completer
Abort” Status when the PEXSTS.RTA is set since the MCH acts as a virtual
PCI bridge and passes the completion abort from the primary to the secondary
side.
Note however that the MCH will not set the SSTAS field directly on the
secondary side since all requests are passed upstream through the primary
side to the internal core logic for decoding.
SDEVT: DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0
SMDPERR: Master Data Parity Error
This bit is set by the PCI Express port on the secondary side (PCI Express
link) if the Parity Error Response Enable bit (PRSPEN) in the Section 3.8.8.28
is set and either of the following two conditions occurs:
•The PCI Express port receives a Completion marked poisoned
•The PCI Express port poisons a write Request
If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to
Table 3-33 for details on the data parity error handling matrix in the Intel 5000P
Chipset MCH.
SFB2BTC: Fast Back-to-Back Transactions Capable
Not applicable to PCI Express. Hardwired to 0.
Reserved. (by PCI SIG)
S66MHCAP: 66 MHz capability
Not applicable to PCI Express. Hardwired to 0.
Reserved. (by PCI SIG)
Table 3-33. Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data Parity Error RAS
Handling
Register Name
PCISTS[15].DPE¹
PCISTS[8].MDPERR
SECSTS[15].SDPE
SECSTS[8].SMDPERR
OB Post OB Compl IN Post IB Compl
yes
yes
no
no
no
yes
no
no
no
no
yes
yes
no
no
no
yes
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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