QG5000XSL9TH Datasheet, PDF (137/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
60h
Intel 5000Z Chipset
4-7
0
60h
Intel 5000P Chipset
Bit
31:16
15
Attr
RV
RW
14
RW
13:11 RW
10:8 RW
7:0
RW
Default
0000h
0h
0h
0h
0h
0h
Description
Reserved.
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
If TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages. For
level triggered interrupts, this bit reflects the state of the interrupt input if TM
is 1h, then
0: Deassert Messages
1: Assert Messages
These bits are don’t care in IOxAPIC interrupt message data field specification.
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
IV: Interrupt Vector
The interrupt vector (LSB) will be modified by the Intel 5000P Chipset MCH to
provide context sensitive interrupt information for different events that require
attention from the processor. For example, hot-plug, Power Management and
RAS error events.
Depending on the number of Messages enabled by the processor in
Section 3.8.10.3, and Table 3-34 illustrates the breakdown.
Table 3-34. IV Handling and Processing by MCH
Number of Messages
enabled by Software
(MSICTRL.MMEN)
Events
IV[7:0]
1
All
xxxxxxxx¹
2
HP, PM
xxxxxxx0
RAS errors
xxxxxxx1
Notes:
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
and the MCH will not modify any of the “x” bits except the LSB as indicated in the table
as a function of MMEN
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
137