QG5000XSL9TH Datasheet, PDF (232/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
47h, 46h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
47h, 46h
Intel 5000P Chipset
Bit
Attr
Default
Description
6:4
RW
3:0
RW
00
INITPAT: Initialization pattern
“000”=TS0: Training Sequence 0 to last AMB (not valid in “Reset”)
“001”=TS1: Training Sequence 1 to last AMB (not valid in “Reset”)
“010”=TS2: Training Sequence 2 to last AMB (not valid in “Reset”)
“011”=TS3: Training Sequence 3 to last AMB (not valid in “Reset”)
“100”=reserved
“101”=TS2: Training Sequence 2 not to last AMB with NB Merge disabled
(not valid in “Reset”)
“110”=TS2: Training Sequence 2 not to last AMB with NB Merge enabled
(not valid in “Reset”)
“111”=All Ones (valid only in “Reset”)
This pattern is superseded by the “EN” bit.
This field is not used during fast reset.
The note ‘(not valid in “Reset”)’ indicates that is not valid when
FBDST.STATE=”Reset” or “Recovery Reset” and EN=’1’. The note ‘(valid only in
“Reset”)’ indicates that this is valid only when FBDST.STATE=”Reset” or
“Recovery Reset”.
0h
AMBID: Advanced Memory Buffer IDentifier
Driven during the training sequences.
This field is also used during fast reset to identify the last (southernmost)
DIMM.
3.9.23.10 FBDISTS[1:0][1:0] - FB-DIMM Initialization Status
The contents of this register are valid only during “Initialization” states. The thirteen
bits [12:0] correspond to the northbound bit-lanes.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
5Ah, 58h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
5Ah, 58h
Intel 5000P Chipset
Bit
15:13
12:0
Attr
RV
RO
Default
000
0000h
Description
Reserved
PATDET: Pattern Detection
“1” = Pattern recognized.
“0” = Pattern not recognized.
Bit-Lane Status is evaluated at the end of each instance of the pattern
specified by the FBDICMD.EN and FBDICMD.INITPAT fields. Bit-Lane status is
evaluated on each change to the FBDICMD.EN and FBDICMD.INITPAT.Only bits
[2:0] are valid during electrical idle, and only after the FBDRST reset sequence
has been executed.
A recognizable training sequence must contain the FBDICMD.AMBID.
TS1 detection is qualified by test patterns specified in section 4.3 of rev. 0.75
of FBD DFx specification, which defines the “SB/NB_Mapping” (1 bit), the “Test
Parameters” (24 bits), and the “Electrical Stress Pattern”.
232
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet