QG5000XSL9TH Datasheet, PDF (388/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.17.6.6
5.17.6.7
5.17.6.8
Other PLL Characteristics
The PLL VCOs oscillate continually from power-up. The PLL output dividers consistently
track the VCO, providing pulses to the clock trees. Logic that does not receive an
asynchronous reset can thus be reset “synchronously”.
A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not
prove that the entire clock tree is continuous.
Analog Power Supply Pins
The Intel 5000X chipset MCH incorporates seven PLLs. Each PLL requires an Analog
Vcc and Analog Vss pad and external LC filter. Therefore, there will be external LC
filters for the Intel 5000X chipset MCH. IMPORTANT: The filter is NOT to be connected
to board Vss. The ground connection of the filter will be routed through the package
and grounded to on-die Vss.
I/O Interface Metastability
PCI Express can be operated frequency-locked to the core. Flits are fifteen-sixteenths
of the core frequency in 266 MHz mode, three-quarters of the core frequency in
333 MHz mode.
However, the phase between the frequency-locked domains is not controlled. This
scheme results in the possibility of a metastability resonance where, for example, the
commands generated by the core miss setup and hold to I/O every time. This condition
can be tolerated by carefully hardened metastability design.
5.18
Error List
This section provides a summary of errors detected by the Intel 5000X chipset . In the
following table, errors are listed by the unit / interfaces. Some units / interfaces may
provide additional error logging registers.
The following table provides the list of detected errors of a the MCH.
Table 5-31. Intel 5000X chipset Error List (Sheet 1 of 7)
ERR #
in MCH
Error Name
Definition
Error
Type
F1
Request/
MCH monitors the address Fatal
Address Parity and request parity signals
Error
on the FSB. A parity
discrepancy over these
fields during a valid
request. MCH only detects
this error caused by CPUs.
F2
Unsupported MCH detected an FSB
Fatal
Request or
Unsupported transaction.
data size on
MCH only detects this error
FSB.
caused by CPUs.
F5
Outstanding
MCH detected that a
Fatal
Deferred FSB previously deferred FSB txn
transaction
has not completed with
has timed out Defer Reply within a
specified time frame.
Log Register
Cause / Actions
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB,
NRECFSB_ADDRH,
NRECFSB_ADDRL for FERR
only.
Complete transaction on FSB
with response (non-hard fail
response)
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only.
Treat as NOP. No Data
Response or Retry by MCH
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only
An access issued on the FSB
has timed out.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet