QG5000XSL9TH Datasheet, PDF (160/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.14 ESICTRL[0] - ESI Control Register
The ESICTRL register holds control information and defeature bits pertaining to the ESI
interface for power management.
3.8.12
3.8.12.1
Device:
Function:
Offset:
Version:
0
0
D4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:15
14
Attr
RV
RW
13:12
11
RV
RWC
10:9 RW
8:4
RV
3:0
RW
Default
0h
1
0
0
0h
0h
0h
Description
Reserved.
DL23R: Override L23 Ready - Recommend setting this bit to 1.
0: Wait for PME_Enter_L23 on all PCIe* ports
1: Do not wait for PME_Enter_L23 on all PCIe ports
Reserved
PTE: PME_TO_Ack Time Expired
0: Default mode, “PME_TO_Ack” message received on all PCI Express ports
before timeout.
1: Signal that time expiration has occurred when the PTOV field described
below crosses the threshold in the Intel 5000P Chipset MCH.
PTOV: PME_TO_Ack Time Out Value
00: 1 ms (default)
01: 10 ms
10: 50 ms
11: Reserved
This register field provides the timer limit for the Intel 5000P Chipset MCH to
keep track of the elapsed time from sending “PME_Turn_off” to receiving a
“PME_TO_Ack”.
Reserved.
SAC: STOPGRANT ACK COUNT
This field tracks the number of Stop Grant acks received from the FSBs. The
MCH will forward the last StopGrantAck received from the FSB to the Intel
631xESB/632xESB I/O Controller Hub using the “Req_C2” command. Software
is expected to set this field to “THREADs-1” where the variable “THREAD” is
the total number of logical threads present in the system (currently can handle
up to 16). Typically each CPU thread will issue a StopGrantAck in response to a
STPCLK# assertion from the Intel 631xESB/632xESB I/O Controller Hub.
When the final StopGrantAck is received from the FSB and the internal counter
hits the value of SAC+1 (which is equal to THREAD), the MCH will initiate the
“Req_C2” command on the DMI.
It is illegal for the CPU to send more Stop Grant Acks than that specified in the
“THREAD” variable.
Note: For Sx Power management in H/W or S/W mode
PCI Express Advanced Error Reporting Capability
PEXENHCAP[7:2, 0] - PCI Express Enhanced Capability Header
This register identifies the capability structure and points to the next structure.
160
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet