QG5000XSL9TH Datasheet, PDF (84/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.2.4
Device:
Function:
Offset:
Version:
16
0
5Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
1:0
RW
00
LOENABLE2: 0C8000-0CBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C8000-0CBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
PAM3 - Programmable Attribute Map Register 3
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0D 0000h - 0D 7FFFh.
Device:
Function:
Offset:
Version:
16
0
5Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
RV
5:4
RW
3:2
RV
1:0
RW
00
Reserved
00
ESIENABLE3: 0D 4000h - 0D 7FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 4000h -0D 7FFFh.
Bit5 = Write enable, Bit4 = Read enable.
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
00
Reserved
00
LOENABLE3: 0D 0000h - 0D 3FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 0000h -0D 3FFFh.
Bit1 = Write enable, Bit0 = Read enable
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
84
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet