QG5000XSL9TH Datasheet, PDF (371/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.16.2.8
Status Field
For a read cycle, the returned data is preceded by one byte of status. The following
table shows how the status byte bits are defined.
5.16.2.9
Position
7
6
5
4
3:1
0
Description
Internal Time-out.
0 = SMBus request is completed within 2 ms internally
1 = SMBus request is not completed in 2 ms internally.
Ignored.
Internal Master Abort.
0 = No Internal Master Abort Detected.
1 = Detected an Internal Master Abort.
Internal Target Abort.
0 = No Internal Target Abort Detected.
1 = Detected an Internal Target Abort.
Ignored.
Successful.
0 = The last SMBus transaction was not completed successfully.
1 = The last SMBus transaction was completed successfully.
Unsupported Access Addresses
It is possible for an SMBus master to program an unsupported bit combination into the
ADDR registers. The MCH does not support such usage, and may not gracefully
terminate such accesses.
5.16.3 SMB Transaction Pictographs
The Intel 5000X chipset MCH SMBus target interface is targeted to enterprise domains.
The enterprise domain is an extension of the original SMBus desktop domain. The
following drawings are included to describe the SMBus enterprise transactions.
i
Figure 5-29. DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
PEC Disabled)
S
0110_000 W A Cmd = 11000010 A Byte Count = 4 A
Bus Number A Device/Function A Reg Number[15:0] A
Reg Number [7:0] CLOCK STRETCH A P
S 0110_000 W A Cmd = 11000010 A
Sr 0110_000 R A Byte Count = 5 A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
A
Data[7:0]
NP
Figure 5-30. DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled)
S 0110_000 W A Cmd = 11001110 A Byte Count = 8 A
Bus Number A Device/Function A Reg Number[15:8] A Reg Number [7:0] A
Data[31:24]
A
Data[23:16] A
Data[16:8]
A
Data[7:0]
CLOCK STRETCH A P
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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