QG5000XSL9TH Datasheet, PDF (234/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.24
3.9.24.1
Note:
FB-DIMM RAS Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in Table 3-3.
UERRCNT[1:0] - Uncorrectable Error Count
This register implements the “leaky-bucket” counters for uncorrectable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Aliased uncorrectable errors are NOT counted as uncorrectable errors in the
implementation of this register. They are treated as correctable errors and logged in
the CERRCNT register.
3.9.24.2
Note:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
A4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
A4h
Intel 5000P Chipset
Bit
Attr Default
Description
31:28 RWCST
27:24 RWCST
23:20 RWCST
19:16 RWCST
15:12 RWCST
11:8 RWCST
7:4 RWCST
3:0 RWCST
0h RANK7: Error Count for Rank 7
0h RANK6: Error Count for Rank 6
0h RANK5: Error Count for Rank 5
0h RANK4: Error Count for Rank 4
0h RANK3: Error Count for Rank 3
0h RANK2: Error Count for Rank 2
0h RANK1: Error Count for Rank 1
0h RANK0: Error Count for Rank 0
CERRCNT[1:0] - Correctable Error Count
This register implements the “leaky-bucket” counters for correctable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Aliased uncorrectable errors are counted as correctable errors in the implementation of
this register.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet