QG5000XSL9TH Datasheet, PDF (144/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.5
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
74h
Intel 5000Z Chipset
4-7
0
74h
Intel 5000P Chipset
Bit
Attr
Default
Description
2
RW
1
RW
0
RW
0
FERE: Fatal Error Reporting Enable
This bit controls the reporting of fatal errors internal to the MCH in the PCI
Express port.
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
0
NFERE: Non Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the MCH in the PCI
Express port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
0
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the MCH in the
PCI Express port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
PEXDEVSTS[7:2, 0] - PCI Express Device Status Register
The PCI Express Device Status register provides information about PCI Express device
specific parameters associated with this port.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
76h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
76h
Intel 5000Z Chipset
4-7
0
76h
Intel 5000P Chipset
Bit
15:6
5
Attr
RV
RO
Default
000h
0h
Description
Reserved.
TP: Transactions Pending
1: Indicates that the PCI Express port has issued Non-Posted Requests which
have not been completed.
0: A device reports this bit cleared only when all Completions for any
outstanding Non-Posted Requests have been received.
Since the MCH Root port that do not issue Non-Posted Requests on their own
behalf, it is hardwired to 0b.
144
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet