QG5000XSL9TH Datasheet, PDF (135/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.10.3 MSICTRL[7:2, 0] - Message Control Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
5Ah
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
5Ah
Intel 5000Z Chipset
4-7
0
5Ah
Intel 5000P Chipset
Bit
15:8
7
Attr
RV
RO
6:4
RW
3:1
RO
0
RW
Default
00h
0
000
001
0
Description
Reserved.
AD64CAP: 64-bit Address Capable
This field is hardwired to 0h since the message writes addresses are only 32-
bit addresses (for example, FEEx_xxxxh).
MMEN: Multiple Message Enable
Software writes to this field to indicate the number of allocated messages
which is aligned to a power of two. When MSI is enabled, the software will
allocate at least one message to the device. See below for discussion on how
the interrupts are handled if N is the number of messages by software.
If software writes a value greater than the limit specified by the MMCAP field in
the MMEN field, it is considered as a programming error. The Intel 5000P
Chipset MCH GNB will only use the LSB of the MMEN (as a power of 2) to
decode up to 2 messages.
MMCAP: Multiple Message Capable
Software reads this field to determine the number of requested messages.
which is aligned to a power of two. It is set to 2 messages (encoding of 001).
The Intel 5000P Chipset MCH is designed to handle MSIs for different events
• HP/PM events
• RAS Error events
MSIEN: MSI Enable
The software sets this bit to select legacy interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the Intel 5000P Chipset MCH to use MSI messages to request
context specific service through register bits defined in the Section 3.8.8.32
for events such as hot-plug, PM, RAS.
Refer to the Intel 5000P Chipset Programming Guide for details on the legacy,
ACPI and interrupt generation events.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
135