QG5000XSL9TH Datasheet, PDF (206/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
16
1
48h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
31
RV
30:28 RW
27:22 RW
21:16 RW
15:8 RW
7:4
RW
3:0
RW
0
Reserved
0h TAL: Additive Latency for Posted CAS
This parameter is the posted-CAS “t_AL” DDR2 timing parameter. It must match the
value written to the EMRS register in the DRAM.
0h TWRC: Activate command to activate command delay following a DDR
write
This parameter is the minimum delay from an activate command followed by a
write with page-close to another activate command on the same bank. This
parameter prevents bank activation protocol violations in the DRAM’s. This
parameter is defined as follows: tRCD + (tCL – 1) + BL/2 + tWR + tRP where t_RCD
is the DDR ras-to-cas delay, t_CL is the cas-to-first-read-data latency, BL is the burst
length, t_WR is the write recovery time, and tRP is the precharge time.This
parameter is defined in core cycles. This parameter is set to greater than or equal
to the largest TWRC of any DIMM on the branch.
0h TRC: Activate command to activate command delay (same bank)
This parameter is the minimum delay from an activate command to another
activate or refresh command to the same bank. This parameter ensures that the
page of the bank that was opened by the first activate command is closed before
the next activate command is issued. This parameter is defined in core cycles. This
parameter is set to greater than or equal to the largest TRC of any DIMM on the
branch.
00h TRFC: Refresh command to activate command delay
This parameter is the minimum delay from a refresh command to another activate
or refresh command. This parameter ensures that the banks that were opened by
the refresh command are closed before the next activate command is issued. This
parameter is defined in core cycles. This parameter is set to greater than or equal
to the largest TRFC of any DIMM on the branch.
0h TRRD: Activate command to activate command delay (different banks)
This parameter is the minimum delay from an activate command to another
activate or refresh command to a different bank on the same rank. This parameter
ensures that the electrical disturbance to the SDRAM die caused by the first activate
has attenuated sufficiently before the next activate is applied. This parameter is
defined in core cycles. This parameter is set to greater than or equal to the largest
TRRD of any DIMM on the branch.
0h TREF: Refresh command to Refresh command delay
This parameter is the maximum delay from a refresh command to another refresh
command to the same rank. This parameter ensures that a sufficient number of
refreshes per time interval are issued to each rank. This parameter is defined as an
integral multiple of FBD super frames. An FBD super frame is 42 FBD packets (1:1,
5:4) or 40 FBD packets for 4:5 gear ratios in the Intel 5000P Chipset.
This parameter is set to less than or equal to the smallest TREF of any DIMM on the
memory sub-system. The refresh interval is typically 7.80 us for a DDRII DIMM
rank.
Refer to Table 3-45, “Optimum TREF values as a function of core: FBD gear ratios
(in FBD Super frames)”.
The refresh period is calculated as follows:
DIMM refresh period = TREF * Super_Frame_size * 8 * FBD clock period where the
number “8” is a constant denoting the maximum number of ranks supported by the
Intel 5000P Chipset.
As an example, the refresh period is given as 7 * 42 * 8 * 3 ns = 7056 ns for a
DDRII667 system with an FSB to FBD ratio of 1:1
A value of zero disables refresh and clears the refresh counter, allowing a test
program to align refresh events with the test and thus improve failure repeatability.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet