QG5000XSL9TH Datasheet, PDF (110/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.11
SUBUSN[7:2] - Subordinate Bus Number
This register identifies the subordinate bus (if any) that resides at the level below the
secondary PCI Express interface. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices subordinate to the
secondary PCI Express port.
3.8.8.12
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
1Ah
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Ah
Intel 5000Z Chipset
4-7
0
1Ah
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RW
00h
SUBBUSNUM: Subordinate Bus Number
This register is programmed by configuration software with the number of the
highest subordinate bus that is behind the PCI Express port.
SEC_LT[7:2] - Secondary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the secondary interface. It does not affect/influence PCI Express functionality.
3.8.8.13
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
1Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Bh
Intel 5000Z Chipset
4-7
0
1Bh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
Slat_tmr: Secondary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
IOBASE[7:2] - I/O Base Register
The I/O Base and I/O Limit registers (see Section 3.8.8.14) define an address range
that is used by the PCI Express port to determine when to forward I/O transactions
from one interface to the other using the following formula:
IO_BASE <= A[15:12]<=IO_LIMIT
110
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet