QG5000XSL9TH Datasheet, PDF (182/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13
3.8.13.1
3.8.13.2
.
Device: 7-2, 0
Function: 0
Offset: 170h
Bit
Attr
7:1
RV
0
RWCST
Default
0h
0
Description
Reserved
SSErr: Stop and Scream Error for PCI Express port
Records the occurrence of the first stop and scream error on the PCI
Express port if this bit is clear.
Error Registers
This section describes the registers that record the first and next errors, logging,
detection masks, signalling masks, and error injection control. The FERR_GLOBAL (first
error register) is used to record the first error condition. The NERR_GLOBAL register is
used to record subsequent errors.
The contents of FERR_GLOBAL and NERR_GLOBAL are “sticky” across a reset (while
PWRGOOD remains asserted). This provides the ability for firmware to perform
diagnostics across reboots. Note that only the contents of FERR_GLOBAL affects the
update of the any error log registers.
FERR_GLOBAL - Global First Error Register
The first fatal and/or first non-fatal errors are flagged in the FERR_GLOBAL register,
subsequent errors are indicated in the NERR_GLOBAL register.
NERR_GLOBAL - Global Next Error Register
Once an error has been logged in the FERR_GLOBAL, subsequent errors are logged in
the NERR_GLOBAL register.
Device:
Function:
Offset:
Version:
16
2
44h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
31
RWCST
30
RWCST
29
RWCST
28
RWCST
27:25
24
RV
RWCST
23
RWCST
22
RWCST
Default
0
0
0
0
0
0
0
0
Description
Global_NERR_31:
Internal Fatal Error
Global_NERR_30:
DMA Engine Device Fatal Error
Global_NERR_29:
FSB1 Fatal Error
Global_NERR_28:
FSB 0 Fatal Error
Reserved
Global_NERR_24:
FB-DIMM Channel 0,1,2 or 3 Fatal Error
Global_NERR_23:
PCI Express Device 7 Fatal Error
Global_NERR_22:
PCI Express Device 6 Fatal Error
182
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet