QG5000XSL9TH Datasheet, PDF (308/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-2. Minimum Two DIMM Configuration
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
BRANCH 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 3
BRANCH 1
Memory Controller
Figure 5-3 depicts the next two positions where DIMMs may be added. These positions
are depicted in dark gray. The two upgrade positions are Branch 0, Slot 1 and Branch 1,
Slot 0. Of these Branch 1, Slot 0 is the preferred upgrade because it allows both
branches to operate independently and simultaneously. FB-DIMM memory bandwidth is
doubled when both branches operate in parallel.
While it is possible to completely populate one branch before populating the second
branch, it is not desirable to do so from a performance standpoint. In general memory
upgrades should be balanced with respect to both branches to optimize FB-DIMM
performance.
Figure 5-3. Next Two DIMM Upgrade Positions
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
BRANCH 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 3
BRANCH 1
Memory Controller
Figure 5-4 depicts a special single DIMM non-mirrored operation mode. This mode
requires that the DIMM be placed in Branch 0, Channel 0, Slot 0. When upgrading from
this mode the normal two DIMM memory upgrade rules are followed.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet