QG5000XSL9TH Datasheet, PDF (103/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.1
PCICMD[7:2, 0]- Command Register
This register defines the PCI 2.3 compatible command register values applicable to PCI
Express space.
Device:
Function:
Offset:
Version:
0, 2-3
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
4-5
Function: 0
Offset:
04h
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
04h
Intel 5000P Chipset
Bit
15:11
10
Attr
RV
RW
9
RO
8
RW
7
RO
6
RW
5
RO
4
RO
3
RO
Default
0h
0
0
0
0
0
0
0
0
Description
Reserved. (by PCI SIG)
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
This bit does not affect the ability of the GNB to route interrupt messages
received at the PCI Express port. However, this bit controls the generation
of legacy interrupts to the DMI for PCI Express errors detected internally in
this port (for example, Malformed TLP, CRC error, completion time out, and
so forth) or when receiving root port error messages or interrupts due to
HP/PM events generated in legacy mode within the Intel 5000P Chipset
MCH. Refer to the INTP register in Section 3.8.8.27, “INTP[7:2,0] -
Interrupt Pin Register” on page 119 for interrupt routing to DMI.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
SERRE: SERR Message Enable
his field handles the reporting of fatal and non-fatal errors by enabling the
error pins ERR[2:0].
1: The GNB is enabled to send fatal/non-fatal errors.
0: TheGNB is disabled from generating fatal/non-fatal errors.
The errors are also enabled by the PEXDEVCTRL register in
Section 3.8.11.4.
In addition, for Type 1 configuration space header devices, for example,
Virtual P2P bridge), this bit, when set, enables transmission of
ERR_NONFATAL and ERR_FATAL error messages¹ forwarded from the PCI
Express interface. This bit does not affect the transmission of forwarded
ERR_COR messages. Refer to the Intel 5000P Chipset MCH RAS Error
Model.
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express. Hardwired to 0.
PERRE: Parity Error Response Enable
When set, this field enables parity checking.
VGAPSE: VGA palette snoop Enable
Not applicable to PCI Express. Hardwired to 0.
MWIEN: Memory Write and Invalidate Enable
Not applicable to PCI Express. Hardwired to 0.
SCE: Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
103