QG5000XSL9TH Datasheet, PDF (169/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
120h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
120h
Intel 5000Z Chipset
4-7
0
120h
Intel 5000P Chipset
Bit
31:0
Attr
ROST
Default
0h
Description
HDRLOGDW1: Header of TLP (DWORD 1) associated with error
3.8.12.13 HDRLOG2[7:2, 0] - Header Log 2
This register contains the third 32 bits of the header log.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
124h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
124h
Intel 5000Z Chipset
4-7
0
124h
Intel 5000P Chipset
Bit
31:0
Attr
ROST
Default
0h
Description
HDRLOGDW2: Header of TLP (DWORD 2) associated with error
3.8.12.14 HDRLOG3[7:2, 0] - Header Log 3
This register contains the fourth 32 bits of the header log.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
128h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
128h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
128h
Intel 5000P Chipset
Bit
31:0
Attr
ROST
Default
0h
Description
HDRLOGDW3: Header of TLP (DWORD 3) associated with error
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
169