QG5000XSL9TH Datasheet, PDF (155/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
84h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
84h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
84h
Intel 5000P Chipset
Bit
Attr
Default
Description
1
RW
0
RW
0h
PWRINTEN: Power Fault Detected Enable
This bit enables the generation of hot-plug interrupts or wake messages via a
power fault event.
0: Disables generation of hot-plug interrupts or wake messages when a power
fault event happens.
1: Enables generation of hot-plug interrupts or wake messages when a power
fault event happens.
0h
ATNINTEN: Attention Button Pressed Enable
This bit enables the generation of hot-plug interrupts or wake messages via an
attention button pressed event.
0: Disables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
1: Enables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
3.8.11.11 PEXSLOTSTS[7:2, 0] - PCI Express Slot Status Register
The PCI Express Slot Status register defines important status information for
operations such as hot-plug and Power Management.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
86h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
86h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
86h
Intel 5000P Chipset
Bit
15:7
6
Attr
RV
RO
Default
0h
1h
Description
Reserved.
PDS: Presence Detect State
This field conveys the Presence Detect status determined via an in-band
mechanism or through the Present Detect pins and shows the presence of a
card in the slot.
0: Slot Empty
1: Card Present in slot
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
155