QG5000XSL9TH Datasheet, PDF (246/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 22
Function: 0
Offset: 294h, 194h
Bit Attr
Default
13:10 RWST
0h
9:0 RWST
001h
Description
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
3.9.25.12 FBD[1:0]IBTXSHFT: Intel IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device: 21
Function: 0
Offset: 294h, 194h
Bit
31:14
Attr
RV
13:10 RWST
9:0 RWST
Default
0h
0h
001h
Description
Reserved
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
3.9.25.13 FBD[3:2]IBRXSHFT: Intel IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device: 22
Function: 0
Offset: 298h, 198h
Bit
31:14
Attr
RV
13 RWST
Default
0h
0
Description
Reserved
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet