QG5000XSL9TH Datasheet, PDF (253/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
7Ch, 78h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
7Ch, 78h
Intel 5000P Chipset
Bit Attr Default
Description
31:28 RWST
27 RWST
26:24 RWST
23:16 RWST
15:8 RWST
7:1
RV
0 RWST
1010
1
000
00h
00h
0h
0
DTI: Device Type Identifier.
This field specifies the device type identifier. Only devices with this device-type will
respond to commands. “1010” specifies EEPROM’s. “0110” specifies a write-protect
operation for an EEPROM. Other identifiers can be specified to target non-EEPROM
devices on the SPD bus.
CKOVRD: Clock Override.
‘0’ = Clock signal is driven low, overriding writing a ‘1’ to CMD.
‘1’ = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to “move” the port out of a “stuck” state.
SA: Slave Address.
This field identifies the DIMM EEPROM to be accessed through the SPD register.
BA: Byte Address.
This field identifies the byte address to be accessed through the SPD register.
DATA: Data.
Holds data to be written by SPDW commands.
Reserved
CMD: Command.
Writing a ‘0’ to this bit initiates an SPDR command. Writing a ‘1’ to this bit initiates
an SPDW command.
DMA Engine Configuration Registers
3.10.1 PCICMD: PCI Command Register
Device:
Function:
Offset:
Version:
8
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
15:11 RV
0h
10
RW
0
9
RO
0
Reserved
INTxDisable: Interrupt Disable
This bit controls the ability of the DMA engine device to assert a legacy PCI
interrupt during DMA completions or DMA errors.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
This bit does not apply to the DMA engine Device and hardwired to 0.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
253