QG5000XSL9TH Datasheet, PDF (304/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
• Snoop-Filter Fast array initialization and/or self test through configuration register
access.
5.2.1
Snoop Filter Address Bit Mapping
The SF supports a 40-bit physical address. Table 5-1 shows the partitioning of the
address for indexing into the SF array.
Table 5-1.
Snoop Filter Physical Address Partitioning
Tag (21b)
A[39:19]
Set (13b)
A[18:6]
Byte Offset (6b)
A[5:0]
5.2.2
Operations and Interfaces
The following table shows the snoop-filter look up qualifier for coherent transaction
issued from processors, i.e. ADS# assertion driven from processors.
Table 5-2. FSB transaction encoding qualification for SF look up
SF look up transactions from FSB:
The following REQa[2:0] encoding with ADS#
assertion from processor qualification.
Request Names
REQa[2:0]
BRIL/BIL
0
1
0
BRLC
1
0
0
BRLD/BLR
1
1
0
BWL
1
0
1
BWIL/BLW
1
1
1
Table 5-1, “Snoop Filter” on page 302 shows the organization of each snoop filter entry,
and interpretation of the contents.
Table 5-3.
Snoop Filter Entry
Bits
[31]
Redundant bit.
[30:24
]
ECC check bits
Value
304
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet