QG5000XSL9TH Datasheet, PDF (373/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-35. DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC
Disabled)
S
0110_000
WA
Cmd = 10100001
A
Dest Mem
A
Add Offset[23:16] A P
S
0110_000
WA
Cmd = 01100001
A
Add Offset[15:8]
A
Add Offset[7:0]
CLOCK STRETCH A P
S
0110_000
WA
Cmd = 10100001
A
Sr
0110_000
RA
Status
A
Data[31:24]
NP
S
0110_000
WA
Cmd = 00100001
A
Sr
0110_000
RA
Data[23:16]
A
Data[15:8]
NP
S
0110_000
WA
Cmd = 01100000
A
Sr
0110_000
RA
Data[7:0]
NP
Figure 5-36. WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled)
S
0110_000
WA
Cmd = 10001000
A
Bus Number
AP
S
0110_000
WA
Cmd = 00001000
A
Device/Function
AP
S
0110_000
WA
Cmd = 00001000
A Register Num[15:8] A P
S
0110_000
WA
Cmd = 00001000
A
Register Num[7:0]
AP
S
0110_000
WA
Cmd = 00001000
A
S
0110_000
WA
Cmd = 01001000
A
Data[W:X]
Data[Y:Z]
AP
CLOCK STRETCH A P
5.16.4
Slave SM Bus, SM Bus 0
System Management software in a Intel 5000X chipset platform can initiate system
management accesses to the configuration registers via the Slave SM bus, SM Bus 0.
The mechanism for the Server Management (SM) software to access configuration
registers is through a SMBus Specification, Revision 2.0 compliant slave port. Some
Intel 5000X chipset components contain this slave port and allow accesses to their
configuration registers. The product specific details are compatible with the Intel
631xESB/632xESB I/O Controller Hub SMBus configuration access mechanism. Most of
the Intel 5000X chipset MCH registers can be accessed through the SMBus
configuration mechanism.
SMBus operations are made up of two major steps:
1. Writing information to registers within each component
2. Reading configuration registers from each component.
The following sections will describe the protocol for an SMBus master to access a Intel
5000X chipset platform component’s internal configuration registers. Refer to the
SMBus Specification, Revision 2.0 for the bus protocol, timings, and waveforms.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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