QG5000XSL9TH Datasheet, PDF (210/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.22
3.9.22.1
Device:
Function:
Offset:
Version:
16
1
94h, 90h, 8Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:0
Attr
RW
Default
0000h
Description
ADJLIMIT: Adjusted MIR Limit
FB-DIMM Error Registers
FERR_FAT_FBD - FB-DIMM First Fatal Errors
The first fatal error for an FB-DIMM branch is flagged in these registers. Only one flag is
ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
channels. Higher-order error bits within a register have higher priority than lower-order
bits. The FBDChan_Indx field is not an error. This register will display invalid index
channel data until an error has occurred.
3.9.22.2
Device:
Function:
Offset:
Version:
16
1
98h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:30
29:28
27:3
2
1
0
Attr
RV
RV
RV
RWCST
RWCST
RWCST
Default
Description
00
00
0000000h
0
0
0
Reserved
FBDChan_Indx: Logs channel in which the error occurred
Reserved
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on non-redundant retry
M1Err: Alert on non-redundant retry or fast reset timeout
NERR_FAT_FBD - FB-DIMM Next Fatal Errors
If an error is already flagged in FERR_FAT_FBD, subsequent and lower-priority fatal
errors are logged in NERR_FAT_FBD.
3.9.22.3
Device:
Function:
Offset:
Version:
16
1
9Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:3
2
1
0
Attr Default
Description
RV
RWCST
RWCST
RWCST
0h
Reserved
0
M3Err: >Tmid Thermal event with intelligent throttling disabled
0
M2Err: Northbound CRC error on non-redundant retry
0
M1Err: Alert on non-redundant retry or fast reset timeout
FERR_NF_FBD - FB-DIMM First Non-Fatal Errors
The first non-fatal error for a FB-DIMM branch is flagged in these registers. Only one
flag is ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
210
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet