QG5000XSL9TH Datasheet, PDF (320/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-9. Code Layout for Single-Channel Branches
x8 x8 x8 x8 x8 x8 x8 x8 x8
CB
[7:0]
DQ[71:0]
DRAMs
DIMMChannel 0
Transfer 0
Transfer 1
Transfer 0
Transfer 1
C
S
1
A
C
S
0
A
D
S
1
5
A
D
S
1
4
A
D
S
1
3
A
D
S
1
2
A
D
S
1
1
A
D
S
1
0
A
D
S
9
A
D
S
8
A
D
S
7
A
D
S
6
A
D
S
5
A
D
S
4
A
D
S
3
A
D
S
2
A
D
S
1
A
D
S
0
A
C
S
1
B
C
S
0
B
D
S
1
5
B
D
S
1
4
B
D
S
1
3
B
D
S
1
2
B
D
S
1
1
B
D
S
1
0
B
D
S
9
B
D
S
8
B
D
S
7
B
D
S
6
B
D
S
5
B
D
S
4
B
D
S
3
B
D
S
2
B
D
S
1
B
D
S
0
B
C
S
3
A
C
S
2
A
D
S
3
1
A
D
S
3
0
A
D
S
2
9
A
D
S
2
8
A
D
S
2
7
A
D
S
2
6
A
D
S
2
5
A
D
S
2
4
A
D
S
2
3
A
D
S
2
2
A
D
S
2
1
A
D
S
2
0
A
D
S
1
9
A
D
S
1
8
A
D
S
1
7
A
D
S
1
6
A
C
S
3
B
C
S
2
B
D
S
3
1
B
D
S
3
0
B
D
S
2
9
B
D
S
2
8
B
D
S
2
7
B
D
S
2
6
B
D
S
2
5
B
D
S
2
4
B
D
S
2
3
B
D
S
2
2
B
D
S
2
1
B
D
S
2
0
B
D
S
1
9
B
D
S
1
8
B
D
S
1
7
B
D
S
1
6
B
Data
Bits
DS0 DS0 DS0 DS0
[3] [2] [1] [0]
DS0
[7]
DS0
[6]
DS0
[5]
DS0
[4]
D[131] D[130] D[129] D[128]
DQ[3] DQ[2] DQ[1] DQ[0]
TRANSFER
0
D
C_S
D
D_S
DDDDDDDD
1 _S1 _S1 _SSSSSSSS
2
3
5
C^A
S
D
S
2
A
D
S
9630
ADADADA
SSS
4
5
10
AA
1
4
A
1
3
A
1
1
A
1
0
A
875421
AAAAAA
Packet 0
6
D
C_S
D
D_S
DDDDDDDD
7 _S1 _S1 _SSSSSSSS
8
9
5
C^B
S
D
S
2
B
D
S
9630
BDBDBDB
SSS
1
0
1
1
10
BB
1
4
B
1
3
B
1
1
B
1
0
B
875421
BBBBBB
0
D
C_S
D
D_S
D
D_S
D
D_S
D
D_S
D
D_S
1 _S3_S2_S2_S2_S1_S1
2
1
C^A
D
8
A
D
5
A
D
2
A
D
9
A
D
6
A
3_{S S S S S S}
4
5
32
AA
3
0
A
2
9
A
2
7
A
2
6
A
2
4
A
2
3
A
2
1
A
2
0
A
1
8
A
1
7
A
Packet 1
6
D
C_S
D
D_S
D
D_S
D
D_S
D
D_S
D
D_S
7 _S3_S2_S2_S2_S1_S1
8
1
C^B
D
8
B
D
5
B
D
2
B
D
9
B
D
6
B
9_{S S S S S S}
1
0
1
1
32
BB
3
0
B
2
9
B
2
7
B
2
6
B
2
4
B
2
3
B
2
1
B
2
0
B
1
8
B
1
7
B
FFFFFFFFFFFF
DDDDDDDDDDDD
000000000000
NNNNNNNNNNNN
BBBBBBBBBBBB
yyyyyyyyyyyy
119876543210
10
FBD
Signals
y=[P:N]
D[0]
D[1]
D[2]
D[3]
D[128]
D[129]
D[130]
D[131]
D[n+2]
D[n+3]
D[n]
D[n+1]
FD0NBy[0]
DS0
[0]
DS0
[1]
DS0
[2]
DS0
[3]
DS1
[0]
DS1
[1]
DS0
[4]
DS0
[5]
DS0
[6]
DS0
[7]
DS1
[4]
DS1
FBDChannel 0
[5]
F
D
0
N
B
FBD
Signal
y
0
DRAMpins
320
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet