QG5000XSL9TH Datasheet, PDF (7/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

5.17
5.18
5.16.1 Internal Access Mechanism .................................................................... 367
5.16.2 SMBus Transaction Field Definitions ........................................................ 368
5.16.3 SMB Transaction Pictographs ................................................................. 371
5.16.4 Slave SM Bus, SM Bus 0........................................................................ 373
5.16.5 FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4 ...................................... 378
5.16.6 PCI Express Hot-Plug Support, SM Bus 6 ................................................. 379
5.16.7 Hot-Plug Controller ............................................................................... 380
5.16.8 PCI Express Hot-Plug Usage Model.......................................................... 380
5.16.9 Virtual Pin Ports ................................................................................... 381
Clocking......................................................................................................... 384
5.17.1 Reference Clocks.................................................................................. 384
5.17.2 JTAG .................................................................................................. 386
5.17.3 SMBus Clock........................................................................................ 386
5.17.4 GPIO Serial Bus Clock ........................................................................... 386
5.17.5 Clock Pins ........................................................................................... 386
5.17.6 High Frequency Clocking Support ........................................................... 387
Error List........................................................................................................ 388
6 Testability ............................................................................................................. 395
6.1 JTAG Port ....................................................................................................... 395
6.1.1 JTAG Access to Configuration Space........................................................ 395
6.1.2 TAP Signals ......................................................................................... 395
6.1.3 Accessing the TAP Logic ........................................................................ 396
6.1.4 Reset Behavior of the TAP ..................................................................... 398
6.1.5 Clocking the TAP .................................................................................. 398
6.1.6 Accessing the Instruction Register .......................................................... 398
6.1.7 Accessing the Data Registers ................................................................. 400
6.1.8 Public TAP Instructions.......................................................................... 400
6.1.9 Public Data Instructions ........................................................................ 401
6.1.10 Public Data Register Control................................................................... 402
6.1.11 Bypass Register ................................................................................... 402
6.1.12 Device ID Register................................................................................ 402
6.1.13 Boundary Scan Register ........................................................................ 403
6.2 Extended Debug Port (XDP) .............................................................................. 404
7 Electrical Characteristics ....................................................................................... 405
7.1 Absolute Maximum Ratings............................................................................... 405
7.1.1 Thermal Characteristics......................................................................... 405
7.1.2 Power Characteristics............................................................................ 405
7.2 DC Characteristics ........................................................................................... 406
7.2.1 Clock DC Characteristics........................................................................ 407
7.2.2 FSB Interface DC Characteristics ............................................................ 408
7.2.3 FB-DIMM DC Characteristics .................................................................. 409
7.2.4 PCI Express/ ESI Interface DC Characteristics .......................................... 410
7.2.5 Miscellaneous DC Characteristics ............................................................ 411
8 Ballout and Package Information........................................................................... 413
8.1 Intel 5000X Chipset MCH Ballout ....................................................................... 413
8.2 Package Information........................................................................................ 455
Figures
1-1 Intel® 5000X Chipset System Block Diagram ........................................................ 21
2-1 Intel 5000X Chipset Clock and Reset Requirements.............................................. 35
2-2 Power-Up ......................................................................................................... 36
2-3 PWRGOOD ....................................................................................................... 36
2-4 Hard Reset ....................................................................................................... 37
2-5 RESETI# Retriggering Limitations ........................................................................ 37
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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