QG5000XSL9TH Datasheet, PDF (205/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.16
GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double
Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. This primarily affects the Northbound data path of the 4:5 config and
determines when both the lanes in core contain valid FB-DIMM data.
Device:
Function:
Offset:
Version:
16
1
16Fh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0 RWST
0h
FBDHSTDBLMUX: FB-DIMM to Host Double Mux Selector
Configures when both data lines are valid according to Table 3-44. This
primarily affect the 4:5 gearing ratio.
Table 3-44. FB-DIMM to Host Double Config Mux Select
FSB:Memory Frequency
Gear Ratio¹
Value
333:333
1:1
267:267
400:400
333:267
5:4
00h
00h²
267:333
4:5 (conservative)
08h
267:333
4:5 (aggressive)
04h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by MGr registers in the 5:4 mode.
3.9.17 Summary of Memory Gearing Register operating modes
• FBDTOHOSTGRCFG1, GRFBDVLDCFG, and GRFBDTOHOSTDBLCFG are used only in
4:5 mode.
• GRBUBBLECFG is only used in 5:4 mode.
• GRHOSTFULLCFG is used in both 4:5 and 5:4 modes.
• FBDTOHOSTGRCFG0 and HOSTTOFBDGRCFG are used in 4:5, 5:4, AND 1:1 modes.
3.9.18
DRTA - DRAM Timing Register A
This register defines timing parameters for all DDR2 SDRAMs in the memory
subsystem. The parameters for these devices are obtained by serial presence detect.
This register must be set to provide timings that satisfy the specifications of all DRAMs
detected. For example, if DRAMs present have different TRCs, the maximum should be
used to program this register. Consult the JEDEC DDR2 DRAM specifications for the
technology of the devices in use.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
205