QG5000XSL9TH Datasheet, PDF (83/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.2.2
3.8.2.3
PAM1 - Programmable Attribute Map Register 1
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 0000h-0C 7FFFh.
Device:
Function:
Offset:
Version:
16
0
5Ah
Intel 5000P Chipset, Intel 5000V Chipset
Bit
Attr
Default
Description
7:6
RV
5:4
RW
3:2
RV
00
Reserved
00
ESIENABLE1: 0C4000-0C7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C4000 to 0C7FFF
Bit5 = Write enable, Bit4 = Read enable.
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
00
Reserved
1:0
RW
00
LOENABLE1: 0C0000-0C3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C0000 to 0C3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
PAM2 - Programmable Attribute Map Register 2
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 8000h -0C FFFF h.
Device:
Function:
Offset:
Version:
16
0
5Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
RV
5:4
RW
3:2
RV
00
Reserved
00
ESIENABLE2: 0CC000-0CFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0CC000-0CFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
00
Reserved
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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