QG5000XSL9TH Datasheet, PDF (225/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.22.26 RECFBDE - Recoverable FB-DIMM Error Log Register E
This register latches information on the first detected non-fatal northbound CRC error.
Device: 16
Function: 1
Offset: FCh
Bit
31:28
27:0
Attr
RV
ROST
Default
0h
0h
Description
Reserved
BITS: Bits [155:128] of the packet
3.9.23
3.9.23.1
FB-DIMM Branch Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in Table 3-3.
FBDLVL[1:0][1:0] - FB-DIMM Packet Levelization
This register controls the FB-DIMM channel delays.
3.9.23.2
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
45h, 44h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
45h, 44h
Intel 5000P Chipset
Bit Attr Default
Description
7:6
RV
5:0
RO
00 Reserved
0h TRRL: Read Round-Trip Latency
Measured from issue of the FB-DIMM channel’s southbound TS2 packet header to
the arrival of its northbound response header.
FBDHPC[1:0]: FBD State Control
This register controls the FBD channel for Initialization and Mirroring Recovery. It
consists of a next State field.
The index in FBDHPC[index] associates the FBDHPC with branch[index]. FBDHPC[0] is
associated with FBD branch 0, FBDHPC[1] is associated with FBD branch 1.
When software writes to FBDHPC[x].NEXTSTATE, the transition will take effect on one
or both channels within the branch depending on whether the branch is operating is
single- or dual-channel mode.
When BNB hardware transitions FBDST.STATE with the following encodings: 1)
disabled, 2) redundant, 3) recovery failed, 4) redundancy loss, and 5) reset, it will
transition states of one or both channels within the same branch depending on whether
the branch is operating in single- or dual-channel mode.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
225