QG5000XSL9TH Datasheet, PDF (9/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

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DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC Disabled)...... 373
WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled) .................. 373
SMBus Configuration Read (Block Write / Block Read, PEC Enabled) ....................... 375
SMBus Configuration Read (Word Writes / Word Reads, PEC Enabled) .................... 376
SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ...................... 376
SMBus Configuration Write (Block Write, PEC Enabled) ......................................... 376
SMBus Configuration Write (Word Writes, PEC Enabled)........................................ 377
SMBus Configuration Write (Write Bytes, PEC Enabled)......................................... 377
Random Byte Read Timing................................................................................ 378
Byte Write Register Timing ............................................................................... 379
PCI Express Hot-Plug/VPP Block Diagram............................................................ 382
Simplified TAP Controller Block Diagram ............................................................. 396
TAP Controller State Machine ............................................................................ 397
TAP Instruction Register ................................................................................... 399
TAP Instruction Register Operation .................................................................... 399
TAP Instruction Register Access......................................................................... 400
TAP Data Register ........................................................................................... 401
Bypass Register Implementation ....................................................................... 402
Intel 5000X Chipset Quadrant Map .................................................................... 413
Intel 5000X Chipset MCH Ballout Left Side (Top View) .......................................... 414
Intel 5000X Chipset MCH Ballout Center (Top View) ............................................. 415
Intel 5000X Chipset MCH Ballout Right Side (Top View) ........................................ 416
Bottom View................................................................................................... 455
Top View........................................................................................................ 456
Package Stackup ............................................................................................. 457
Notes ............................................................................................................ 458
Tables
1-1 General Terminology.......................................................................................... 13
2-1 Signal Naming Conventions ................................................................................ 24
2-2 Buffer Signal Types ........................................................................................... 24
2-3 Power Up and Hard Reset Timings ....................................................................... 38
2-4 Critical Intel® 5000P Initialization Timings ........................................................... 39
3-1 Configuration Address Bit Mapping....................................................................... 49
3-2 Memory Control Hub ESI Device Identification ....................................................... 49
3-3 Functions Specially Handled by the MCH............................................................... 50
3-4 Access to “Non-Existent” Register Bits.................................................................. 51
3-5 I/O Address: CF8h............................................................................................. 51
3-6 I/O Address: CFCh ............................................................................................ 52
3-7 Mapping for Fixed Memory Mapped Registers ........................................................ 52
3-8 Device 0, Function 0: PCI Express PCI Space ........................................................ 53
3-9 Device 0, Function 0: PCI Express Extended Registers............................................ 54
3-10 Device 0, Function 0: PCI Express Intel® Interconnect BIST
(Intel® IBIST) Registers .................................................................................... 55
3-11 Device 2-3, Function 0: PCI Express PCI Space ..................................................... 56
3-12 Device 2-3, Function 0: PCI Express Extended Registers......................................... 57
3-13 Device 2-3, Function 0: PCI Express Intel IBIST Registers....................................... 58
3-14 Device 4, Function 0: PCI Express PCI Space ........................................................ 59
3-15 Device 4, Function 0: PCI Express Extended Registers............................................ 60
3-16 Device 4, Function 0: PCI Express Intel IBIST Registers.......................................... 61
3-17 Device 5-7, Function 0: PCI Express PCI Space ..................................................... 62
3-18 Device 5-7, Function 0: PCI Express Extended Registers......................................... 63
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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