QG5000XSL9TH Datasheet, PDF (385/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
is common to both PCI Express agents, no phase matching between them is required
(plesiochronous mode). The Intel 5000X chipset MCH core treats this frequency
domain asynchronously.
The BUSCLK and FBDCLK reference clocks are derived from the same oscillator. The
PECLK reference clock may be derived from a different oscillator.
The PCI Express interfaces operate asynchronously with respect to the core clock.
Table 5-27. Intel 5000X Chipset MCH Frequencies for Processors and Core
Core
133 MHz
266 MHz
333 MHz
333 MHz
Domain
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
Frequency
133 MHz
266 MHz
533 MHz
266 MHz
533 MHz
1,067 MHz
167 MHz
333 MHz
667 MHz
333 MHz
667 MHz
1333 MHz
Reference
Clock
BUSCLK
Table 5-28. Intel 5000X Chipset MCH Frequencies for Memory
DDR
533 MHz
667 MHz
800 MHz
Domain
FBD U
FBD packet
FBDCLK
FBD U
FBD packet
FBDCLK
FBD U
FBD packet
FBDCLK
Frequency
3.2 GHz
266 MHz
133 MHz
4.0 GHz
333 MHz
167 MHz
4.8 GHz
400 MHz
200 MHz
Reference
Clock
FBDCLK
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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