QG5000XSL9TH Datasheet, PDF (122/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
3Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Eh
Intel 5000Z Chipset
4-7
0
3Eh
Intel 5000P Chipset
Bit
Attr
Default
Description
3
RW
2
RW
1
RW
0
RW
0
VGAEN: VGA Enable
Controls the routing of CPU initiated transactions targeting VGA compatible I/
O and memory address ranges. This bit may only be set for one PCI Express
port.
0
ISAEN: ISA Enable
Modifies the response by the Intel 5000P Chipset MCH to an I/O access issued
by the CPU that target ISA I/O addresses. This applies only to I/O addresses
that are enabled by the IOBASE and IOLIM registers.
1: The Intel 5000P Chipset MCH will not forward to PCI Express any I/O
transactions addressing the last 768 bytes in each 1KB block even if the
addresses are within the range defined by the IOBASE and IOLIM registers.
See Section 4.5.2. Instead of going to PCI Express these cycles will be
forwarded to ESI where they can be subtractively or positively claimed by the
ISA bridge.
0: All addresses defined by the IOBASE and IOLIM for CPU I/O transactions
will be mapped to PCI Express.
0
BCSERRE: SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express port to the primary side.
1: Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages.
0: Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL.
Note that BCSERRE is no longer a gating item for the recording of the
SESCSTS.SRSE error.
0
PRSPEN: Parity Error Response Enable
This bit controls the response to poisoned TLPs in the PCI Express port
1: Enables reporting of poisoned TLP errors.
0: Disables reporting of poisoned TLP errors
122
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet