QG5000XSL9TH Datasheet, PDF (290/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
Table 4-5.
Intel 5000X chipset MCH Memory Mapping Registers (Sheet 2 of 2)
Name
Function
MLIMIT (dev 2-7)
Limit address for memory mapped I/O to PCI Express ports 2 - 7.
PMBASE (dev 2-7)
Base address for memory mapped I/O to prefetchable memory of PCI Express
ports 2-7¹
PMLIMIT (dev 2-7)
Limit address for memory mapped I/O to prefetchable memory of PCI Express
ports 2-7.
PMBU (dev 2-7)
Prefetchable Memory Base (Upper 32 bits) - Upper address bits to the base
address of prefetchable memory space. If the prefetchable memory is below 4 GB,
this register will be set to all 0’s.
PMLU (dev 2-7)
Prefetchable Memory Limit (Upper 32 bits) - Upper address bits to the limit address
of prefetchable memory space. If the prefetchable memory is below 4 GB, this
register will be set to all 0’s.
PCICMD (dev 2-7)
MSE (Memory Space Enable) bit enables the memory and prefetchable ranges.
Notes:
1. The chipset treats memory and prefetchable memory the same. These are just considered 2 apertures to the
PCI Express port.
4.4.2
Address Disposition for Processor
The following tables define the address disposition for the Intel 5000X chipset MCH.
Table 4-6 defines the disposition of outbound requests entering the Intel 5000X chipset
MCH on the processor bus. Table 4-10 defines the disposition of inbound requests
entering the Intel 5000X chipset MCH on an I/O bus. For address dispositions of PCI
Express/ESI devices, please refer to the respective product specifications for the
Intel 6700PXH 64 bit PCI Hub or Intel 631xESB/632xESB I/O Controller Hub.
Table 4-6.
Address Disposition for Processor (Sheet 1 of 2)
Address
Range
DOS
SMM/VGA
C and D BIOS
segments
Conditions
Intel 5000P Chipset Behavior
0 to 09FFFFh
0A0000h to 0BFFFFh
0C0000h to 0DFFFFh and PAM=11
Write to
0C0000h to 0DFFFFh and PAM=10
Read to
0C0000h to 0DFFFFh and PAM=01
Read to
0C0000h to 0DFFFFh and PAM=10
Write to
0C0000h to 0DFFFFh and PAM=01
0C0000h to 0DFFFFh and PAM=00
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
see Table 4-8 and Table 4-9.
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Issue request to ESI.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet