QG5000XSL9TH Datasheet, PDF (112/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.15
K
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
1Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Dh
Intel 5000Z Chipset
4-7
0
1Dh
Intel 5000P Chipset
Bit
Attr
Default
Description
3:0
RO
0h
IOLCAP: I/O Address Limit Capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
others - Reserved.
The MCH does not support 32 bit I/O addressing, so these bits are hardwired to
0.
SECSTS[7:2] - Secondary Status
SECSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express side) of the “virtual” PCI-PCI
bridge embedded within MCH.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
1Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Eh
Intel 5000Z Chipset
4-7
0
1Eh
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RWC
14
RWC
0
SDPE: Detected Parity Error
This bit is set by the Intel 5000P Chipset MCH whenever it receives a poisoned
TLP in the PCI Express port regardless of the state the Parity Error Response
bit (in the BCTRL.PRSPEN register).
BCTRL.PRSPEN register). This corresponds to IO4 as defined in Table 5-31,
“Intel 5000X chipset Error List” on page 388.
0
SRSE: Received System Error
This bit is set by the MCH when it receives a ERR_FATAL or ERR_NONFATAL
message. Section 3.8.8.28. (Note that BCTRL.BCSERRE is not a gating item
for the recording of this error on the secondary side).
13
RWC
0
SRMAS: Received Master Abort Status
This bit is set when the PCI Express port receives a Completion with
“Unsupported Request Completion” Status.
112
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet