QG5000XSL9TH Datasheet, PDF (361/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.13.9.1
Credit Update Mechanism, Flow Control Protocol (FCP)
After reset, credit information is initialized with the values indicated in Table 5-16 by
following the flow control initialization protocol defined in the PCI Express Base
Specification, Revision 1.0a. Since the MCH supports only VC0, only this channel is
initialized.
5.13.10 Transaction Layer
The PCI Express Transaction Layer is responsible for sending read and write operations
between components. This is the PCI Express layer which actually moves software
visible data between components. The transaction layer provides the mechanisms for:
• Software configuration of components
• Communication between the processor bus and different I/O technologies
• Communication between the memory and different I/O technologies
Figure 5-17 illustrates the scope of the transaction layer on a PCI Express packet.
Some transaction layer packets have only a header (for example, read request). Some
transaction layer packets have a header followed by data (for example, write requests
and read completions).
Figure 5-25. PCI Express Packet Visibility By Transaction Layer
Hdr
Hdr
Payload
5.14
5.14.1
Power Management
The Intel 5000X chipset MCH power management support includes:
• ACPI supported
• System States: S0, S1 (desktop), S3, S4, S5, C0, C1, C2 (desktop)
Supported ACPI States
The MCH supports the following ACPI States:
• Processor
— C0: Full On.
— C1: Auto Halt.
— C2 Desktop: Stop Grant. Clock to processor still running. Clock stopped to
processor core.
• System
— G0/S0: Full On.
— G1/S1: Stop Grant, Desktop S1, same as C2.
— G1/S2: Not supported.
— G1/S3: Suspend to RAM (STR). Power and context lost to chipset.
— G1/S4: Suspend to Disk (STD). All power lost (except wake-up logic on Intel
631xESB/632xESB I/O Controller Hub).
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
361