QG5000XSL9TH Datasheet, PDF (173/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
144h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
144h
Intel 5000Z Chipset
4-7
0
144h
Intel 5000P Chipset
Bit
31:8
Attr
RV
7:6
RW
5:4
RW
3:2
RW
1:0
RW
Default
0h
00
00
00
00
Description
Reserved.
PEX_RP_FAT_MAP: Root Port steering for fatal errors
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port Fatal errors are routed to one of the ERR[2:0] pins or MCERR.
PEX_RP_NF_MAP: Root Port steering for non-fatal errors
00: ERR[0],
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port Non Fatal (uncorrectable) errors are routed to one of the
ERR[2:0] pins or MCERR.
PEX_RP_CORR_MAP: Root Port steering for correctable errors
00: ERR[0],
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port correctable errors are routed to one of the ERR[2:0] pins or
MCERR.
PEX_DEV_UNSUP_MAP:
Report steering for unsupported request errors (master aborts) for legacy
devices.
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
Unsupported request error report enable is in the Device control register. This
is Error IO2.
3.8.12.20 EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI
This register masks (blocks) the detection of the selected error bits for the ESI port.
When a specific error is blocked, it does NOT get reported or logged.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
173