QG5000XSL9TH Datasheet, PDF (343/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-15. PCI Express Hot-Plug Interrupt Flow
PEXHPINT
(PEXCTRL.HPGPE
EN == 1)
Y
Intel® 5000P Chipset
Sends assert_HPGPE
message via DMI
N
Intel® 5000P Chipset
sends desassert_HPGP
E message via
DMI when the
respective bits of
PEXSLOTSTS str
cleared (wired-
OR)
PEXSLOTCTRL[x].
N
HPINTEN = 1?
SW polls
status
Y
(MSICTRL[x].
MSIEN == 1) ?
N
PEXCMD[x].INTx
Disable == 1?
Y
Intel® 5000P Chipset
Y
sends MSI
per MSIAR and
MSIDR
Intel® 5000P Chipset
N
Sends assert_INTx
message via DMI
per INTP
Intel® 5000P Chipset
Sends desassert_INTx
message via DMI
when the
respective bits of
PEXSLOTSTS str
cleared (wired-
OR)
HPGPEEN
1
0
0
0
0
HPINTEN
x
1
1
1
0
MSIEN
x
1
0
0
x
INTx Disable
x
x
0
1
x
Output
assert_hpgpe
MSI
assert_intx
--
--
4. PCI Hot-Plug - Chipset will receive an Assert/Deassert GPE message from the PCI
Express port when a PCI Hot-Plug event is happening. Assert/Deassert GPE
messages should be treated the same as Assert/Deassert GPE messages for PCI
Express Hot-Plug. (Keep track of Assert/Deassert GPE messages from each port
and send Assert_GPE, Deassert_GPE message to ESI appropriately)
5. PCI Express Power management - PCI Express sends a PME message. Chipset
sends Assert_PMEGPE to ESI port when a power management event is detected.
a. Upon receipt of the PME message, Intel 5000X chipset MCH will set the
PEXRTSTS.PMESTATUS bit corresponding to that port and send Assert_PMEGPE
to ESI port to generate the interrupt. (Assert_PMEGPE should be sent if one or
more of the PMESTATUS bits are set and enabled.) To generate an SCI (ACPI),
this message will be used by the Intel 631xESB/632xESB I/O Controller Hub to
drive appropriate pin. When software has completed servicing the power
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
343