QG5000XSL9TH Datasheet, PDF (172/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
134h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
134h
Intel 5000Z Chipset
4-7
0
134h
Intel 5000P Chipset
Bit
31:16
Attr
ROST
15:0 ROST
Default
0h
0h
Description
ERR_FAT_NOFAT_SID: Fatal No Fatal Error Source ID Requestor ID of
the source when an Fatal or No Fatal error is received and the
ERR_FAT_NOFAT_RCVD bit is not already set. i.e log ID of the first Fatal or
Non Fatal error
ERR_CORR_SID: Correctable Error Source ID
Requestor ID of the source when a correctable error is received and the
ERR_CORR_RCVD is not already set. i.e log ID of the first correctable error.
3.8.12.18 Intel 5000P Chipset MCH SPCAPID[7:2, 0] - MCH Specific Capability ID
This register identifies the capability structure and points to the next structure.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
140h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
140h
Intel 5000Z Chipset
4-7
0
140h
Intel 5000P Chipset
Bit
31:20
Attr
RO
19:16 RO
15:0 RO
Default
0h
0h
0h
Description
NXTCAPOFF: Next Capability Offset
This field points to the next Capability in extended configuration space. It is
set 000h since this is the final structure in the chain.
VN: Version Number
Version number for this capability structure.
EXTCAPID: Extended CAP_ID
3.8.12.19 PEX_ERR_DOCMD[7:2, 0] - PCI Express Error Do Command Register
Link Error Commands for doing the various signaling: ERR[2:0] and MCERR.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet