QG5000XSL9TH Datasheet, PDF (273/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.11.7
PEX[7:2,0]IBDLYSYM: PEX Intel IBIST Delay Symbol
This register stores the value of the delay symbol used in lane inversion cross-talk
testing. Only valid PCI Express control characters/symbols are allowed for Intel IBIST
testing.
3.11.8
Device: 3-2, 0
Function: 0
Offset: 38Ch
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
38Ch
Intel 5000Z Chipset
Device: 7-4
Function: 0
Offset: 38Ch
Version: Intel 5000P Chipset
Bit
15:9
8:0
Attr Default
Description
RV
0h Reserved
DLYSYM: Delay Symbol
RW
1BCh
This is the 9-bit delay symbol value used (default is K28.5).
PEX[7:2,0]IBLOOPCNT: PEX Intel IBIST Loop Counter
This register stores the current value of the loop counter.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
3-2, 0
0
38Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
38Eh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
7-4
0
38Eh
Intel 5000P Chipset
Bit
15:12
11:0
Attr
RV
RO
Default
Description
0h
000h
Reserved
LOOPCNTVAL: Loop Count Value
Once the Intel IBIST is engaged, loop counts are incremented when a set of 8
symbols has been received. If an error occurs, this register reflects the loop count
value of the errant Rx lane. If there is no error then this register reads 00h.
Note: Since each receiver is not deskewed with respect to the Intel IBIST pattern
generator we cannot have a coherent loop count value with N number of receivers
and only one loop counter. It would require additional logic to select which
receiver indicates the count.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
273