QG5000XSL9TH Datasheet, PDF (372/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-31. DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC
Disabled)
S
0110_000 W A Cmd = 11100010 A Byte Count = 4 A Destination Mem A Add Offset[23:16] A Add Offset[15:8] A Add Offset[7:0] CLOCK STRETCH A P
S
0110_000 W A Cmd = 11100010 A
Sr 0110_000 R A Byte Count = 5 A
Status
A
Data[31:24]
A
Data[23:16] A
Data[15:8]
A
Data[7:0]
NP
Figure 5-32. DWORD Memory Write Protocol
S 0110_000 W A Cmd = 11101110 A Byte Count = 8 A Destination Mem A Add Offset[23:16] A Add Offset[15:8] A Add Ofset[7:0] A
A
Data[23:16]
A
Data[16:8]
A
Data[7:0]
CLOCK STRETCH A P
Data[31:24]
Figure 5-33. DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
PEC Disabled)
S
0110_000
WA
Cmd = 10000001
A
Bus Number
A
Device/Function
AP
S
0110_000
WA
Cmd = 01000001
A
Register Num[15:8] A
Register Num[7:0] CLOCK STRETCH A P
S
0110_000
WA
Cmd = 10000001
A
Sr
0110_000
RA
Status
A
Data[31:24]
NP
S
0110_000
WA
Cmd = 00000001
A
Sr
0110_000
RA
Data[23:16]
A
Data[15:8]
NP
S
0110_000
WA
Cmd = 01000000
A
Sr
0110_000
RA
Data[7:0]
NP
Figure 5-34. DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled)
S
0110_000
WA
Cmd = 10001101
A
Bus Number
A
Device/Function
AP
S
0110_000
WA
Cmd = 00001101
A Register Num[15:8] A
Register Num[7:0] A P
S
0110_000
WA
Cmd = 00001101
A
Data[31:24]
A
Data[23:16]
AP
S
0110_000
WA
Cmd = 01001101
A
Data[15:8]
A
Data[7:0]
CLOCK STRETCH A P
S
0110_000
WA
Cmd = 10101101
A
Dest Mem
A
Add Offset[23:16] A P
S
0110_000
WA
Cmd = 00101101
A
Add Offset[15:8]
A
Add Offset[7:0] A P
S
0110_000
WA
Cmd = 00101101
A
Data[31:24]
A
Data[23:16]
AP
S
0110_000
WA
Cmd = 01101101
A
Data[15:8]
A
Data[7:0]
CLOCK STRETCH A P
372
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet