QG5000XSL9TH Datasheet, PDF (16/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Table 1-1.
General Terminology (Sheet 4 of 7)
Terminology
LSb
LSB
Master
Master Abort
MB/s
MCH
Mem
Memory Issue
Mesochronous
Metastability
Mirroring
MMIO
MMCFG
MSb
MSB
MTBF
Non-Coherent
Outbound
Outgoing
Packet
Page Hit.
Page Miss (Empty
Page)
Page Replace Aka
Page Miss, Row Hit/
Page Miss.
PCI
PCI 2.3 compliant
Plesiochronous
Posted
Description
Least Significant Bit
Least Significant Byte
A device or logical entity that is capable of initiating transactions. A Master is any
potential Initiator.
A response to an illegal request. Reads receive all ones. Writes have no effect.
Megabytes per second (10⁶ bytes per second)
The Memory Controller Hub component that contains the processor interface, DRAM
controller, PCI Express interface, and AGP interface. It communicates with the I/O
controller hub (Intel 631xESB/632xESB I/O Controller Hub) over a proprietary
interconnect called the Enterprise South Bridge Interface (ESI).
Used as a qualifier for transactions that target memory space. (for example, A Mem
read to I/O).
Committing a request to DDR or, in the case of a read, returning the read header.
Distributed or common referenced clock.
A characteristic of flip flops that describes the state where the output becomes non-
deterministic. Most commonly caused by a setup or hold time violation.
RAID-1. Please see RAID for detail descriptions.
Memory Mapped IO. Any memory access to PCI Express or 3GIOC ports.
Memory Mapped Configuration. A memory transaction that accesses configuration
space.
Most Significant Bit.
Most Significant Byte.
Mean Time Between Failure.
Transactions that may cause the processor's view of memory through the cache to be
different with that obtained through the I/O subsystem.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
A transaction or completion that exits the Intel 5000X chipset. Peer-to-Peer
Transactions that occur between two devices below the PCI Express or ESI ports.
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
An access to an open page, or DRAM row. The data can be supplied from the sense
amps at low latency.
An access to a page that is not buffered in sense amps and must be fetched from
DRAM array. Address Bit Permuting Address bits are distributed among channel
selects, DRAM selects, bank selects to so that a linear address stream accesses these
resources in a certain sequence.
An access to a row that has another page open. The page must be transferred back
from the sense amps to the array, and the bank must be precharged.
Peripheral Component Interconnect Local Bus. A 32-bit or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect
mechanism within a system between processor/memory and peripheral components
or add-in cards.
Refers to compliance to the PCI Local Bus Specification, Revision 2.3.
Each end of a link uses an independent clock reference. Support of this operational
mode places restrictions on the absolute frequency difference, as specified by PCI
Express, which can be tolerated between the two independent clock references.
A transaction that is considered complete by the initiating agent or source before it
actually completes at the target of the request or destination. All agents or devices
handling the request on behalf of the original Initiator must then treat the transaction
as being system visible from the initiating interface all the way to the final destination.
Commonly refers to memory writes.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet