QG5000XSL9TH Datasheet, PDF (8/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

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Simplest Power Good Distribution ........................................................................40
Basic System Reset Distribution...........................................................................40
Basic INIT# Distribution .....................................................................................40
Conceptual Intel® 5000X chipset MCH PCI Configuration Diagram...........................46
Type 1 Configuration Address to PCI Address Mapping ............................................48
Intel 5000P Chipset MCH implementation of SRID and CRID Registers ......................77
PCI Express Configuration Space........................................................................ 102
PCI Express Hot-Plug Interrupt Flow................................................................... 157
FB-DIMM Reset Timing ..................................................................................... 228
Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow............ 261
System Memory Address Map............................................................................ 278
Detailed Memory System Address Map ............................................................... 279
Interrupt /SMM Region ..................................................................................... 286
System I/O Address Space................................................................................ 296
System I/O Address Space................................................................................ 298
Snoop Filter .................................................................................................... 302
Minimum Two DIMM Configuration ..................................................................... 308
Next Two DIMM Upgrade Positions ..................................................................... 308
Single DIMM Operation Mode............................................................................. 309
Minimum Mirrored Mode Memory Configuration.................................................... 309
Mirrored Mode Next Upgrade ............................................................................. 310
FB-DIMM Channel Schematic............................................................................. 311
Connection of DIMM Serial I/O Signals................................................................ 317
Code Layout for Single-Channel Branches ........................................................... 320
Code Layout for Dual-Channel Branches ............................................................. 321
Thermal Throttling with THRMHUNT=1................................................................ 326
Thermal Throttling with THRMHUNT=0................................................................ 326
Thermal Throttling Activation Algorithm .............................................................. 328
XAPIC Address Encoding ................................................................................... 335
PCI Express Hot-Plug Interrupt Flow................................................................... 343
MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge Interface....
347
x4 PCI Express Bit Lane.................................................................................... 350
ESI and PCI Express Ports 2 and 3 ..................................................................... 351
MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations .................. 352
Intel 5000X Chipset PCI Express* High Performance x16 Port ............................... 353
PCI Express Packet Visibility By Physical Layer..................................................... 355
PCI Express Elastic Buffer (x4 Example).............................................................. 356
PCI Express Deskew Buffer (4X Example) ........................................................... 357
PCI Express Packet Visibility By Link Layer .......................................................... 358
PCI Express Packet Visibility By Transaction Layer................................................ 361
Intel 5000P Chipset Power Sequencing ............................................................... 362
Power-On Reset Sequence ................................................................................ 366
MCH SM Bus Interfaces .................................................................................... 367
DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
PEC Disabled) ................................................................................................. 371
DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled) ................ 371
DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC Disabled)....... 372
DWORD Memory Write Protocol ......................................................................... 372
DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
PEC Disabled) ................................................................................................. 372
DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled)................. 372
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet