QG5000XSL9TH Datasheet, PDF (176/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
14Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
14Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
14Ch
Intel 5000P Chipset
Bit
Attr
Default
Description
0
RW
0
IO12DetMsk: Receiver Error Mask
3.8.12.23 EMASK_RP_PEX[7:2, 0] - Root Port Error Detect Mask
This register masks (blocks) the detection of the selected bits associated with the root
port errors. Normally, all are detected.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
150h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
150h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
150h
Intel 5000P Chipset
Bit
31:3
2
1
0
Attr
RV
RW
RW
RW
Default
0h
0
0
0
Description
Reserved
IO1DetMsk: Fatal Message Detect Mask
IO11DetMsk: Uncorrectable Message Detect Mask
IO17DetMsk: Correctable Message Detect Mask
3.8.12.24 PEX_FAT_FERR[7:2, 0] - PCI Express First Fatal Error Register
This register records the occurrence of the first unmasked PCI Express FATAL errors
and written by the MCH if the respective bits are not set prior. The classification of
uncorrectable errors into FATAL is based on the severity level of the UNCERRSEV
register described in Section 3.8.12.7.
176
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet