QG5000XSL9TH Datasheet, PDF (149/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.8
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
7Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
7Ch
Intel 5000P Chipset
Bit
Attr
Default
Description
1:0
RW
00
ASTPMCTRL: Active State Link PM Control
This field controls the level of active state power management supported on
the given PCI Express port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
Note: This has no effect on the Intel 5000P Chipset MCH.
PEXLNKSTS[7:2, 0] - PCI Express Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training, and so forth.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
7Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Eh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
7Eh
Intel 5000P Chipset
Bit
Attr
15:13
12
RV
RWO
Default
0h
1
Description
Reserved.
SCCON: Slot Clock Configuration
This bit indicates that the component uses the same physical reference clock
that the platform provides on the connector. If the device uses an independent
clock irrespective of the presence of a reference on the connector, this bit
must be clear.
1: indicates same physical clock in the PCI Express connector as in the
platform.
0: indicates independent clock on the PCI Express connector from that of the
platform.
The Intel 5000P Chipset MCH initializes this bit to '1' because the expected
state of the platform is to have one clock source shared between the Intel
5000P Chipset MCH component and any down-devices or slot connectors. It is
the responsibility of BIOS to be aware of the real platform configuration, and
clear this bit if the reference clocks differ.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
149