QG5000XSL9TH Datasheet, PDF (106/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.3
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
06h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
06h
Intel 5000Z Chipset
4-7
0
06h
Intel 5000P Chipset
Bit
Attr
Default
Description
8
RWC
7
RO
6
RV
5
RO
4
RO
3
RO
2:0
RV
0
MDPERR: Master Data Parity Error
This bit is set by the PCI Express port if the Parity Error Response Enable bit
(PERRE) is set and it receives error B1, F2, F6, M2 and M4 (uncorrectable
data error or Address/Control parity errors or an internal failure). If the Parity
Error Enable bit (PERRE) is cleared, this bit is never set.
0
FB2B: Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
0
Reserved. (by PCI SIG)
0
66MHZCAP: 66 MHz capable.
Not applicable to PCI Express. Hardwired to 0.
1
CAPL: Capabilities List
This bit indicates the presence of PCI Express capabilities list structure in the
PCI Express port. Hardwired to 1. (Mandatory)
0
INTxSTAT: INTx Status
Indicates that an INTx interrupt message is pending internally in the PCI
Express port.
The INTx status bit should be rescinded when all the relevant events via RAS
errors/HP/PM internal to the port that requires legacy interrupts are cleared by
software.
0h
Reserved. (by PCI SIG)
CLS[7:2, 0] - Cache Line Size
This register contains the Cache Line Size and is set by BIOS/Operating system. It does
not affect the PCI Express port functionality in the MCH.
106
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet