QG5000XSL9TH Datasheet, PDF (143/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
74h
Intel 5000Z Chipset
4-7
0
74h
Intel 5000P Chipset
Bit
Attr
Default
Description
9
RO
0
PFEN: Phantom Functions Enable
This bit enables the PCI Express port to use unclaimed functions as Phantom
Functions for extending the number of outstanding transaction identifiers.
Intel 5000P Chipset MCH does not implement this bit (Root complex) and is
hardwired to 0.
8
RO
0h
ETFEN: Extended Tag Field Enable
This bit enables the PCI Express port to use an 8-bit Tag field as a requester.
The Intel 5000P Chipset MCH does not use this field (Root complex) and is
hardwired to 0.
7:5
RW
000
MPS: Max Payload Size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express port. As a receiver, the Intel 5000P Chipset MCH must
handle TLPs as large as the set value. As a transmitter, it must not generate
TLPs exceeding the set value. Permissible values that can be programmed
are indicated by the Max_Payload_Size_Supported in the Device Capabilities
register:
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
101: 4096B max payload size
others: Reserved
Note: The MCH supports max payload sizes only up to 256B. If Software
programs a value that exceeds 256B for the MPS field, then it will be
considered as an error. For receive TLPs, it will be flagged as “unsupported
request” and for transmit TLPs, it will be recorded as a Malformed TLP.
Note: Due to erratum 501664, read completion coalescing cannot be used if
MPS=256 B is set by software. Read completion combining up to 128 B would
work only if the MPS is set by software. Read completion combining up to
128 B would work only if the MPS is set to 128 B. See
PEXCTRL.COALESCE_EN field.
4
RO
0
ENRORD: Enable Relaxed Ordering
Intel 5000P Chipset MCH enforces only strict ordering only and hence this bit
is initialized to ‘0’
3
RW
0
URREN: Unsupported Request Reporting Enable
This bit controls the reporting of unsupported requests to the MCH in the PCI
Express port.
0: Unsupported request reporting is disabled
1: Unsupported request reporting is enabled
Note that the reporting of error messages (such as ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by PCI Express port is controlled
exclusively by the PCI Express Root Control register (PEXRTCTRL) described
in Section 3.8.11.12.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
143