QG5000XSL9TH Datasheet, PDF (264/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.16 PEXCAPS - PCI Express Capabilities Register
Device:
Function:
Offset:
Version:
8
0
6Eh
Intel 5000P Chipset
Bit Attr Default
Description
15:14 RV
13:9 RO
8
RO
7:4
RO
3:0
RO
0h
0h
0
0000
0001
Reserved
IMN: Interrupt Message Number:
This field indicates the interrupt message number that is generated from the DMA
Engine device. When there are more than one MSI interrupt Number, this register
field is required to contain the offset between the base Message Data and the MSI
Message that is generated when the status bits in the slot status register or root port
status registers are set.
Slot_Impl: Slot Implemented: DMA Engine is an integrated device and therefore a
slot is never implemented.
DPT: Device/Port Type: DMA Engine device represents a PCI Express Endpoint.
VERS: Capability Version: DMA Engine supports Revision 1 of the PCI Express
specification.
3.10.17 PEXDEVCAP - Device Capabilities Register
Device:
Function:
Offset:
Version:
8
0
70h
Intel 5000P Chipset
Bit Attr Default
Description
31:28 RV
0h
27:26 RO
00
25:18 RO
00h
17:15 RV
0h
14
RO
0
13
RO
0
12
RO
0
11:9 RO
000
8:6
RO
000
5
RO
0
4:3
RO
00
Reserved
CSPLS: Captured Slot Power Limit Scale
This field applies only to upstream ports. Hardwired to 0h
CSPLV: Captured Slot Power Limit Value
This field applies only to upstream ports. Hardwired to 0h
Reserved
PIPD: Power Indicator Present
The DMA Engine is an integrated device and therefore, an Power Indicator does not
exist. Hardwired to 0h
AIPD: Attention Indicator Present
The DMA Engine is an integrated device and therefore, an Attention Indicator does
not exist. Hardwired to 0h
ABPD: Attention Button Present
The DMA Engine is an integrated device and therefore, an Attention Button does not
exist. Hardwired to 0h
EPL1AL: Endpoint L1 Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant. Hardwired to 0h
EPL0AL: Endpoint L0s Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant. Hardwired to 0h
ETFS: Extended Tag Field Supported
The DMA Engine device does not support extended tags. Hardwired to 0h
PFS: Phantom Functions Supported
The DMA Engine device does not support Phantom Functions. Hardwired to 0h
264
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet