QG5000XSL9TH Datasheet, PDF (132/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.9.2
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
50h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
50h
Intel 5000Z Chipset
4-7
0
50h
Intel 5000P Chipset
Bit
31:27
Attr
RO
26
RO
25
RO
24:22 RO
21
RO
20
RV
19
RO
18:16 RO
15:8 RO
7:0
RO
Default
11001
0
0
0h
0
0
0
010
58h
01h
Description
PMES: PME Support
Identifies power states in the Intel 5000P Chipset MCH which can send an
“Assert_PMEGPE/Deassert PMEGPE” message. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b - Assert_PMEGPE/Deassert PMEGPE can be sent from D0
XXX1Xb - Assert_PMEGPE/Deassert PMEGPE can be sent from D1 (Not
supported by Intel 5000P Chipset MCH)
XX1XXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D2 (Not
supported by Intel 5000P Chipset MCH)
X1XXXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D3 hot
(Supported by Intel 5000P Chipset MCH)
1XXXXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D3 cold
(Not supported by Intel 5000P Chipset MCH)
D2S: D2 Support
Intel 5000P Chipset MCH does not support power management state D2.
D1S: D1 Support
Intel 5000P Chipset MCH does not support power management state D1.
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
PMECLK: PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
VER: Version
This field is set to 2h as version number from the PCI Express Base
Specification, Revision 1.0a specification.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
PMCSR[7:2, 0] - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the MCH.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet